Some sequential circuits, such as latches and flip-flops, accept an input that is a logical function of multiple inputs; these sequential circuits are typically called functional-input sequential circuits. The logical function of the input signals can be any function such as an OR, NAND, NOR, or AND operation. Typically, implementation of these logical functions requires a series combination of transistors, which increases the input signals setup time, defined as the minimum amount of time before a clock's active edge by which the data must be stable for it to be latched correctly. Any violation in this minimum required time causes incorrect data capture, known as setup violation.
Further, in networks that include a number of sequential elements in a single clock path, the sequential elements face different insertion delays, and therefore, the clock signal reaches the sequential elements at different times. If the setup time of the signals at the sequential elements is different and further, if the sequential elements have varying insertion delays, data can be incorrectly captured, causing errors. In certain situations, the clock can be skewed to compensate for the insertion delays, but if the sequential elements all belong to the same clock path, skewing the clock becomes cumbersome.